1. Field of the Invention
The present invention relates to a receiving apparatus, and more particularly to, a receiving apparatus and method in view of the SerDes Framer Interface Level 5 (SFI-5).
The present invention is derived from a research project supported by the Information Technology (IT) Research & Development (R&D) program of the Ministry of Information and Communication (MIC) and the Institute for Information Technology Advancement (IITA) [2006-S-060-02, Development of OTH-based 40 G Multi-service Transmission Technology].
2. Description of the Related Art
The SerDes Framer Interface Level 5 (SFI-5) is a standardized electrical interface standard defined by the optical internetworking forum (OIF) in order to facilitate communication of several tens of Gbps of very high-speed data signals between devices. According to the SFI-5, each of a sending end and a receiving end communicate 16 several Gpbs data signals that are divided from a several tens of Gpbs data signal. The length of a physical line connected to each of the 16 several Gpbs data signals can be different and thus, a delay of each several Gpbs data signal can be different. The difference in delay between the 16 several Gpbs data signals is referred to as a skew. In order to allow each several Gpbs data signal to have a consistent delay, a receiving apparatus according to the SFI-5 compensates for a skew between the received several Gpbs data signals, and performs signal processing with regard to the several Gpbs data signals having the compensated skew. The receiving apparatus according to the SFI-5 receives a deskew signal that is a signal obtained by multiplexing a sampling value of each several Gpbs data signal, and the 16 several Gpbs data signals, compares each value of the received several Gpbs data signals with a sampling value included in the received deskew signal, calculates a delay of each several Gpbs data signal, and compensates for a skew of the received 16 several Gpbs data signals in view of the delay.
When a plurality of several Gpbs data signals that are divided from a several tens of Gpbs data level according to the SFI-5 are received, it is necessary to design and develop an expensive high-speed application specific integrated circuit (ASIC) in order to receive and process the plurality of several Gpbs data signals. However, since a great amount of time and money are required to design and develop the ASIC, a method of receiving and processing several Gpbs data signals that are divided from a several tens of Gpbs data level according to the SFI-5 is needed.